This invention relates to an RC oscillator.
Circuits intended for monitor applications require definitely superior performance as regards the operating frequency and accuracy of the signals which control sweeping than standard TV circuits. Consequently with such applications an RC oscillator stage with different switch-over thresholds is required which is adequately accurate and performs reliably.
Currently, as a triggerable oscillator, for use with circuits intended for monitor applications, a positive feedback differential amplifier is used. That oscillator comprises a capacitive element which is fed through a resistor, and a differential stage connected with one input thereof to a terminal of the capacitor and with a second input thereof to a point in the circuit at a variable voltage. In particular in the absence of an external control signal, the voltage of the second input varies between an upper threshold and a lower threshold, whereas in the presence of an appropriate external signal, the upper threshold voltage is reduced to vary the time when the capacitor discharge begins, thus obtaining a periodically varying output voltage whose frequency depends, inter alia, on the difference between the upper switch-over threshold and the intermediate one in the presence of the external trigger signal.
A known circuit of that type is shown in FIG. 1 by way of example, FIGS. 2a and 2b showing waveforms relating to some points in the circuit of FIG. 1. In detail, the oscillator comprises a capacitive element C.sub.1 connected at one terminal thereof (where the output voltage V.sub.C is tapped) to a feed resistor R.sub.1. The remainder of the circuit forms the oscillator control section, adapted to control and vary the durations of the charge and discharge phases of the capacitor, and therefore, to vary the oscillation frequency of the circuit. That control section comprises substantially a differential stage, generally designated with the reference numeral 1, consisting of four transistors Q.sub.1,Q.sub.2,Q.sub.3 and Q.sub.4. Such transistors, of the PNP type, are arranged such that the base of the transistor Q.sub.2 is connected to the emitter of the transistor Q.sub.1, and the base of the transistor Q.sub.3 is connected to the emitter of Q.sub.4. The emitters of Q.sub.2 and Q.sub.3 are connected to each other and to a bias current source I.sub.1. The base of Q.sub.1 is connected to the circuit output terminal, and the base of the transistor Q.sub.4 is connected to the point V.sub.S whereat the threshold voltage is present which causes switching-over in the various operation phases of the circuit. The collectors of Q.sub.1 and Q.sub.4 are grounded, and the collectors of Q.sub.2 and Q.sub.3 are connected respectively to a diode-connected transistor Q.sub.7 and to a transistor Q.sub.8 forming a current mirror.
The control section further comprises a transistor Q.sub.5 which maintains the discharge of C.sub.1 and having the collector connected to V.sub.C, the emitter connected to ground through a resistor R.sub.2 and the base connected to the common point of the collectors of Q.sub.3 and Q.sub.8. Connected to the same point is the base of a further transistor Q.sub.6 adapted to set the lower switch-over threshold of the circuit. The transistor Q.sub.6 has the emitter grounded and the collector connected in an intermediate point of a voltage divider consisting of resistors R.sub.3,R.sub.4,R.sub.5 and R.sub.6. The circuit is completed by a transistor Q.sub.9 to the base whereof trigger pulses V.sub.T are applied.
The operation of the circuit of FIG. 1 is as follows. In the absence of a trigger pulse V.sub.T, the transistor Q.sub.9 is off. Consequently, the threshold switch-over voltage V.sub.S depends on the state of the transistor Q.sub.6. In particular with the transistor Q.sub.6 off, an upper threshold voltage is obtained: ##EQU1## whilst with the transistor Q.sub.6 saturated, the lower threshold voltage is given by: ##EQU2## on the contrary, in the presence of the trigger pulse V.sub.T, the transistor Q.sub.9 is saturated and the upper threshold voltage V.sub.S is given by: ##EQU3## Let us assume than that the trigger pulse V.sub.T is absent and the capacitor C.sub.1 is discharged (V.sub.C =0). Consequently, the transistors Q.sub.1,Q.sub.2,Q.sub.7 and Q.sub.8 are conducting, whereas the transistors Q.sub.3,Q.sub.4,Q.sub.5 and Q.sub.6 are off. In this phase, on the base of Q.sub.4 there is present the upper threshold voltage V.sub.S'. Consequently, the capacitor C.sub.1 begins to become charged through the resistor R.sub.1 until it reaches the switch-over threshold V.sub.S', on exceeding which the transistors Q.sub.1 and Q.sub.2 turn off, whereas the transistors Q.sub.3 and Q.sub.4 switch into conduction. Consequently, the current mirror Q.sub.7 and Q.sub.8 switches off and the collector current Q.sub.3 brings Q.sub.5 into conduction (which thus causes the fast discharge of the capacitor) as well as Q.sub.6 (which sets the lower threshold V.sub.L). Then, the capacitor begins the discharge until the voltage V.sub.C again reaches the lower switch-over threshold V.sub.L. On reaching that threshold, the transistors Q.sub.3 and Q.sub.4 switch off, Q.sub.1 and Q.sub.2 go into conduction activating the current mirror Q.sub.8 and Q.sub.9 which causes Q.sub.5 and Q.sub.6 to switch off. From this time on the cycle is repeated as previously described.
When at the base of the transistor Q.sub.9, one or more trigger pulses V.sub.T are applied, the transistor Q.sub.9 goes into conduction and, therefore, the threshold voltage V.sub.S at the base of Q.sub.4 drops to the value determined by V.sub.S". Therefore the discharge of C.sub.1 is no more triggered by V.sub.S ', but occurs at the positive edge of the trigger pulse. The resulting output voltage of the known oscillator is shown in FIG. 2a in dependence on the trigger voltage V.sub.T.
While commonly employed, the device just described has some drawbacks. In fact, since the low switch-over threshold V.sub.L depends on the saturating voltage V.sub.CE 6 sat, the amplitude of the resulting waveform V.sub.C and hence the free frequency f.sub.o of the output signal are dependent on the process tolerances and vary as the operating temperature varies. Consequently, the circuit has not the desired accuracy.
Another disadvantage of the circuit according to the prior art resides in that during charging of C.sub.1 the transistors Q.sub.1 and Q.sub.2 are conducting and the base delivered current is supplied to the capacitor C.sub.1, adding to the charge current set through R.sub.1. Since the base current of Q.sub.1 is variable due to the differences in tolerance of the value of .beta. and the different operating temperatures, the circuit presents an error on the desired free frequency f.sub.o.
Finally, not to be neglected is the fact that, owing to the use of PNP transistors to control switching between the charge and discharge phases of the capacitor, and in view of the intrinsic speed limitations of transistors of that type, the maximum operating frequency is restricted to set values.